World Library  

Add to Book Shelf
Flag as Inappropriate
Email this Book

A Vlsi Design Concept for Parallel Iterative Algorithms : Volume 7, Issue 8 (18/05/2009)

By Sun, C. C.

Click here to view

Book Id: WPLBN0003973939
Format Type: PDF Article :
File Size: Pages 6
Reproduction Date: 2015

Title: A Vlsi Design Concept for Parallel Iterative Algorithms : Volume 7, Issue 8 (18/05/2009)  
Author: Sun, C. C.
Volume: Vol. 7, Issue 8
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection (Contemporary), Copernicus GmbH
Publication Date:
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications


APA MLA Chicago

Sun, C. C., & Götze, J. (2009). A Vlsi Design Concept for Parallel Iterative Algorithms : Volume 7, Issue 8 (18/05/2009). Retrieved from

Description: Dortmund University of Technology, Information Processing Lab, Otto-Hahn-Str. 4, 44227 Dortmund, Germany. Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

A VLSI design concept for parallel iterative algorithms

Ahmedsaid, A., Amira, A., and Bouridane, A.: Improved SVD systolic array and implementation on FPGA, in: IEEE International Conference on Field-Programmable Technology (FPT), pp. 3–42, 2003.; Brent, R P. and Luk, F T.: The Solution of Singular-Value and Symmetric Eigenvalue Problems on Multiprocessor Arrays, SIAM Journal on Scientific and Statistical Computing, 6, 69–84, 1985.; Gelsinger, P.: Moore's Law: We See No End in Sight,, Tech. rep., Intel Chief Technology Officer, prefix, 2008.; Goetze, J. and Hekstra, G.: An Algorithm and Architecture Based on Orthonormal Micro-Rotations for Computing the Symmetric EVD, INTEGRATION – The VLSI Journal, 20, 21–39, 1995.; Gotze, J., Paul, S., and Sauer, M.: An Efficient Jacobi-Like Algorithm for Parallel Eigenvalue Computation, IEEE Transactions on Computers, 42, 1058–1065, 1993.; Klauke, S. and Goetze, J.: Low Power Enhancements for Parallel Algorithms, in: IEEE International Symopsium on Circuits and Systems, 2001.; Parhi, K K. and Nishitani, T.: Digial Signal Processing for Multimedia Systems, MARCEL DEKKER, New York, 1999.; Sainarayanan, K S., Raghunandan, C., and Srinivas, M.: Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme, in: IEEE Computer Society Annual Symposium on VLSI, pp. 401–408, 2007.; Stine, J E., Castellanos, I., Wood, M., Henson, J., Love, F., Davis, W R., Franzon, P D., Bucher, M., and Basavarajaiah, S.: FreePDK: An Open-Source Variation-Aware Design Kit, in: IEEE International Conference on Microelectronic Systems Education, pp. 173–174, 2007.; Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y., and Borkar, N.: An 80-Tile 1.28TFLOPS Network-on-Chip in 65 nm CMOS, Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 98–589, 2007.; Vitullo, F., L'Insalata, N. E., Petri, E., Saponara, S., Fanucci, L., Casula, M., Locatelli, R., and Coppola, M.: Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip, IEEE Transactions on Computer, 57, 1196–1201, 2008.; Volder, J.: The CORDIC trigonometric computing technique, IRE Trans. Electron. Comput., EC-8, 330–334, 1959.; Walther, J.: A unified algorithm for elementary functions, in: Proc. Spring Joint Comput. Conf., vol 38, pp. 379–385, 1971.; Wolf, W.: The future of multiprocessor systems-on-chips, in: Annual ACM IEEE Design Automation Conference, pp. 681–685, 2004.


Click To View

Additional Books

  • Different Approaches of High Speed Data ... (by )
  • Obstacle-based Self-calibration Techniqu... (by )
  • Breakdown Behavior of Electronics at Var... (by )
  • Eine Präzise Multilevel-testbench Zur Sy... (by )
  • Kopplung Eines Auf Der Momentenmethode B... (by )
  • Automated Collection and Dissemination o... (by )
  • Design Issues of Arithmetic Structures i... (by )
  • The Asynchronous Rapid Single-flux Quant... (by )
  • A Reconfigurable Software Defined Ultra-... (by )
  • Cost725 – Establishing a European Phenol... (by )
  • A Fully Probe Corrected Near-field Far-f... (by )
  • Radiation Efficient Unidirectional Low-p... (by )
Scroll Left
Scroll Right


Copyright © World Library Foundation. All rights reserved. eBooks from World eBook Library are sponsored by the World Library Foundation,
a 501c(4) Member's Support Non-Profit Organization, and is NOT affiliated with any governmental agency or department.