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A Vlsi Design Concept for Parallel Iterative Algorithms : Volume 7, Issue 8 (18/05/2009)

By Sun, C. C.

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Book Id: WPLBN0003973939
Format Type: PDF Article :
File Size: Pages 6
Reproduction Date: 2015

Title: A Vlsi Design Concept for Parallel Iterative Algorithms : Volume 7, Issue 8 (18/05/2009)  
Author: Sun, C. C.
Volume: Vol. 7, Issue 8
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection (Contemporary), Copernicus GmbH
Historic
Publication Date:
2009
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications

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Sun, C. C., & Götze, J. (2009). A Vlsi Design Concept for Parallel Iterative Algorithms : Volume 7, Issue 8 (18/05/2009). Retrieved from http://www.ebooklibrary.org/


Description
Description: Dortmund University of Technology, Information Processing Lab, Otto-Hahn-Str. 4, 44227 Dortmund, Germany. Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

Summary
A VLSI design concept for parallel iterative algorithms

Excerpt
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