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Countermeasures Against Nbti Degradation on 6T-sram Cells : Volume 9, Issue 18 (01/08/2011)

By Glocker, E.

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Book Id: WPLBN0003983607
Format Type: PDF Article :
File Size: Pages 7
Reproduction Date: 2015

Title: Countermeasures Against Nbti Degradation on 6T-sram Cells : Volume 9, Issue 18 (01/08/2011)  
Author: Glocker, E.
Volume: Vol. 9, Issue 18
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection (Contemporary), Copernicus GmbH
Historic
Publication Date:
2011
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications

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Schmitt-Landsiedel, D., Drapatz, S., & Glocker, E. (2011). Countermeasures Against Nbti Degradation on 6T-sram Cells : Volume 9, Issue 18 (01/08/2011). Retrieved from http://www.ebooklibrary.org/


Description
Description: Lehrstuhl für Technische Elektronik, Technische Universität München, Theresienstraße 90, 80333 München, Germany. In current process technologies, NBTI (negative bias temperature instability) has the most severe aging effect on static random access memory (SRAM) cells. This degradation effect causes loss of stability. In this paper countermeasures against this hazard are presented and quantified via simulations in 90 nm process technologies by the established metrics SNMread, SNMhold, Iread and Write Level. With regard to simulation results and practicability best candidates are chosen and, dependent on individual preferences at memory cell design, the best countermeasure in each case is recommended.

Summary
Countermeasures against NBTI degradation on 6T-SRAM cells

Excerpt
%; [8] Bauer, F.: A Design Space Comparison of 6T and 8T SRAM Core-Cells, in: 18th International Workshop PATMOS 2008, 10–12 September, Revised Selected Papers, Lecture Notes in Computer Science, pp. 116–125, 2009.; %; [2] Drapatz, S., Fischer, T., Hofmann, K., Amirante, E., Huber, P., Ostermayr, M., Georgakos, G., and Schmitt-Landsiedel, D.: Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation, Solid-State Circuits Conference, ESSCIRC 2009, 35th European, pp. 92–95, 2009a.; %; [5] Drapatz, S., Georgakos, G., and Schmitt-Landsiedel, D.: Impact of negative and positive bias temperature stress on 6T-SRAM cells, Adv. Radio Sci., 7, 191–196, doi:10.5194/ars-7-191-2009, 2009b.; %; %; [6] Drapatz, S., Hofmann, K., Georgakos, G., and Schmitt-Landsiedel, D.: Impact of fast-recovering NBTI degradation on stability of large-scale SRAM arrays, Solid-State Device Research Conference, ESSDERC 2010. 40th European, 2010.; [4] Huard, V., Chevallier, R., Parthasarathy, C., Mishra, A., Ruiz-Amador, N., Persin, F., Robert, V., Chimeno, A., Pion, E., Planes, N., Ney, D., Cacho, F., Kapoor, N., Kulshrestha, V., Chopra, S., and Vialle, N.: Managing SRAM reliability from bitcell to library level, in IRPS, IEEE International, 2010.; %; [1] Seevinck, E., List, F. J., and Lohstroh, J.: Static Noise Margin Analysis of MOS SRAM Cells, IEEE Journal of solid-state circuits, SC-22(5), 748–754, 1987.; %; [9] von Arnim, K., Borinski, E., Seegebrecht, P., Fiedler, H., Brederlow, R., Thewes, R., Berthold, J., and Pacha, C.: Efficiency of Body Biasing in 90-nm CMOS for Low-Power Digital Circuits, IEEE Journal of Solid-State Circuits, 40(7), 1549–1556 , 2005.; %; [3] Baoguang Yan, Qingguo Fan, Bernstein, J. B., Jin Qin, and Jun Dai: Reliability simulation and circuit-failure analy- sis in analog and mixed-signal applications, Dev. and Mat. Rel., IEEE Transactions on, 9(3), 339–347 , 2009.; %; [7] Zhang, M.: Performance Comparison of SRAM Cells Implemented in 6, 7 and 8-Transistor Cell Topologies, Electrical and Computer Engineering, University of California, Davis, unpublished data.

 

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