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Impact of Process Variations and Long Term Degradation on 6T-sram Cells : Volume 5, Issue 12 (13/06/2007)

By Fischer, Th.

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Book Id: WPLBN0003988098
Format Type: PDF Article :
File Size: Pages 5
Reproduction Date: 2015

Title: Impact of Process Variations and Long Term Degradation on 6T-sram Cells : Volume 5, Issue 12 (13/06/2007)  
Author: Fischer, Th.
Volume: Vol. 5, Issue 12
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection, Copernicus GmbH
Publication Date:
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications


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Georgakos, G., Lemaitre, B., Schmitt-Landsiedel, D., Fischer, T., & Olbrich, A. (2007). Impact of Process Variations and Long Term Degradation on 6T-sram Cells : Volume 5, Issue 12 (13/06/2007). Retrieved from

Description: Lehrstuhl für Technische Elektronik, Technische Universität München, München, Germany. In modern deep-submicron CMOS technologies voltage scaling can not keep up with the scaling of the dimensions of transistors. Therefore the electrical fields inside the transistors are not constant anymore, while scaling down the device area. The rising electrical fields bring up reliability problems, such as hot carrier injection. Also other long term degradation mechanisms like Negative Bias Temperature Instability (NBTI) come into the focus of circuit design.

Along with process device parameter variations (threshold voltage, mobility), variations due to the degradation of devices form a big challenge for designers to build circuits that both yield high under the influence of process variations and remain functional with respect to long term device drift.

In this work we present the influence of long term degradation and process variations on the performance of SRAM core-cells and parametric yield of SRAM arrays. For different use cases we show the performance degradation depending on temperature and supply voltage.

Impact of process variations and long term degradation on 6T-SRAM cells

ITRS, International Technology Roadmap for Semiconductors 2005 Edition,, 2005.; Alam, M. A.: A Critical Examination of the Mechanics of Dynamic NBTI for PMOSFETs, IEEE Intl. Electron Devices Meeting 2003, p 345, 2003.; Ogawa, S., Shimaya, M., and Shiono, N.: Interface-trap generation at ultrathin $SiO_2$ (4–6 mm)-Si Interfaces during negative-bias temperature aging, J. Appl. Phys., 77(3), 1137–1148, 1995.; Schlunder, C., Brederlow, R., Ankele, B., Lill, A., Goser, K., and Thewes, R.: On the Degradation of P-MOSFETs in Analog and RF Circuits under Inhomogeneous Negative Bias Temperature Stress, 41st Annual Intl. Reliability Physics Symposium 2003, p 5–10, 2005.; Hu, C. M., Tam, S. C., HSU, F., Ko, P., Chan, T., and Terrill, K.: Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Imprpvement, IEEE Trans. Electron Devices, 32(2), 375–385, 1985.; Bravaix, A.: Hot Carrier Degradation Evolution in Deep Submicrometer CMOS Technologies, IEEE IRW, 174–183, 1999.; Seevinck, E., List, F., and Lohstroh, J.: Static Noise Margin Analysis of MOS SRAM Cells, IEEE J. Solid State Circuits, 22(5), 525–536, 1987.; Fischer, Th., Nirschl, T., Lemaitre, B., and Schmitt-Landsiedel, D.: Modelling of the parametric Yield in decnanometer SRAM-Arrays, Adv. Radio Sci., 4, 281–285, 2006.; Antreich, K., Graeb, H., and Wieser, C.: Circuit Analysis and Optimization Driven by Worst Case Distances, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(1), 57–71, 1994.


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